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features ? high-performance, low-power avr ? 8-bit microcontroller ? risc architecture ? 130 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier ? nonvolatile program and data memories ? 8k bytes of in-system self-programmable flash endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-w rite operation ? 512 bytes eeprom endurance: 100,000 write/erase cycles ? 512 bytes internal sram ? up to 64k bytes optional external memory space ? programming lock for software security ? peripheral features ? one 8-bit timer/counter with se parate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? three pwm channels ? programmable serial usart ? master/slave spi serial interface ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated rc oscillator ? external and internal interrupt sources ? three sleep modes: idle, power-down and standby ? i/o and packages ? 35 programmable i/o lines ? 40-pin pdip, 44-lead tqfp, 44 -lead plcc, and 44-pad qfn/mlf ? operating voltages ? 2.7 - 5.5v for atmega8515l ? 4.5 - 5.5v for atmega8515 ? speed grades ? 0 - 8 mhz for atmega8515l ? 0 - 16 mhz for atmega8515 8-bit microcontroller with 8k bytes in-system programmable flash atmega8515 atmega8515l summary 2512js?avr?10/06 note: this is a summary do cument. a complete document is available on our web site at www.atmel.com.
2 atmega8515(l) 2512js?avr?10/06 pin configurations figure 1. pinout atmega8515 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (oc0/t0) pb0 (t1) pb1 (ain0) pb2 (ain1) pb3 (ss) pb4 (mosi) pb5 (miso) pb6 (sck) pb7 reset (rxd) pd0 (tdx) pd1 (int0) pd2 (int1) pd3 (xck) pd4 (oc1a) pd5 (wr) pd6 (rd) pd7 xtal2 xtal1 gnd vcc pa0 (ad0) pa1 (ad1) pa2 (ad2) pa3 (ad3) pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pe0 (icp/int2) pe1 (ale) pe2 (oc1b) pc7 (a15) pc6 (a14) pc5 (a13) pc4 (a12) pc3 (a11) pc2 (a10) pc1 (a9) pc0 (a8) pdip 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 (mosi) pb5 (miso) pb6 (sck) pb7 reset (rxd) pd0 nc* (txd) pd1 (int0) pd2 (int1) pd3 (xck) pd4 (oc1a) pd5 pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pe0 (icp/int2) nc* pe1 (ale) pe2 (oc1b) pc7 (a15) pc6 (a14) pc5 (a13) 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 (wr) pd6 (rd) pd7 xtal2 xtal1 gnd nc* (a8) pc0 (a9) pc1 (a10) pc2 (a11) pc3 (a12) pc4 pb4 (ss) pb3 (ain1) pb2 (ain0) pb1 (t1) pb0 (oc0/t0) nc* vcc pa0 (ad0) pa1 (ad1) pa2 (ad2) pa3 (ad3) tqfp/mlf 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 (mosi) pb5 (miso) pb6 (sck) pb7 reset (rxd) pd0 nc* (txd) pd1 (int0) pd2 (int1) pd3 (xck) pd4 (oc1a) pd5 pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pe0 (icp/int2) nc* pe1 (ale) pe2 (oc1b) pc7 (a15) pc6 (a14) pc5 (a13) 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 (wr) pd6 (rd) pd7 xtal2 xtal1 gnd nc* (a8) pc0 (a9) pc1 (a10) pc2 (a11) pc3 (a12) pc4 pb4 (ss) pb3 (ain1) pb2 (ain0) pb1 (t1) pb0 (oc0/t0) nc* vcc pa0 (ad0) pa1 (ad1) pa2 (ad2) pa3 (ad3) plcc notes: 1. mlf bottom pad should be soldered to ground. 2. * nc = do not connect ( ma y be used in future devices )
3 atmega8515(l) 2512js?avr?10/06 overview the atmega8515 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powe rful instructions in a single clock cycle, the atmega8515 achieves throughputs approaching 1 mips per mhz allowing the sys- tem designer to optimize power cons umption versus processing speed. block diagram figure 2. block diagram internal oscillator watchdog timer mcu ctrl. & timing oscillator timers/ counters interrupt unit stack pointer eeprom sram status register usart program counter program flash instruction register instruction decoder programming logic spi comp. interface porta drivers/buffers porta digital interface general purpose registers x y z alu + - portc drivers/buffers portc digital interface portb digital interface portb drivers/buffers portd digital interface portd drivers/buffers xtal1 xtal2 reset control lines vcc gnd pa0 - pa7 pc0 - pc7 pd0 - pd7 pb0 - pb7 avr cpu internal calibrated oscillator porte drivers/ buffers porte digital interface pe0 - pe2
4 atmega8515(l) 2512js?avr?10/06 the avr core combines a rich instruction se t with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmega8515 provides the following features: 8k bytes of in-system programmable flash with read-while-wri te capabilities, 512 byte s eeprom, 512 bytes sram, an external memory interface, 35 general purpose i/o lines, 32 general purpose working registers, two flexible timer/counters with compare modes, internal and external inter- rupts, a serial programmable usart, a programmable watchdog timer with internal oscillator, a spi serial port, and three software se lectable power saving modes. the idle mode stops the cpu while a llowing the sram, timer/counters, spi port, and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other ch ip functions until the ne xt interrupt or hard- ware reset. in standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. this allows very fast start-up comb ined with low-power consumption. the device is manufactured using atmel?s hi gh density nonvolatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. soft- ware in the boot flas h section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel atmega8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega8515 is su pported with a full suite of program and system development tools including: c compilers, macro assemb lers, program debugger/simulators, in-cir- cuit emulators, and evaluation kits. disclaimer typical values contained in this datasheet are based on simulations and characteriza- tion of other avr microcontrollers manufactured on the same process technology. min and max values will be available afte r the device is characterized. at90s4414/8515 and atmega8515 compatibility the atmega8515 provides all the features of the at90s4414/8515. in addition, several new features are added. the atmega8515 is backward compatible with at90s4414/8515 in most cases. however, some incompatibilities between the two microcontrollers exist. to solve this problem, an at90s4414/8515 compatibility mode can be selected by programming the s8515c fuse. atmega8515 is 100% pin compati- ble with at90s4414/8515, and can replace the at90s4414/8515 on current printed circuit boards. however, the location of fuse bits and the electrical characteristics dif- fers between the two devices. at90s4414/8515 compatibility mode programming the s8515c fuse will change the following functionality: ? the timed sequence for changing the watchdog time-out period is disabled. see ?timed sequences for changing the configuration of the watchdog timer? on page 53 for details. ? the double buffering of the usart receive registers is disabled. see ?avr usart vs. avr uart ? compatib ility? on page 13 7 for details. ? porte(2:1) will be set as output, and porte0 will be set as input.
5 atmega8515(l) 2512js?avr?10/06 pin descriptions vcc digital supply voltage. gnd ground. port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. when pi ns pa0 to pa7 are used as inputs and are externally pulled low, they will sour ce current if the internal pull-up resistors are ac tivated. the port a pins are tri-stated when a reset conditi on becomes active, even if the clock is not running. port a also serves the functions of various special features of the atmega8515 as listed on page 67. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the atmega8515 as listed on page 67. port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port d pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the atmega8515 as listed on page 72. port e(pe2..pe0) port e is an 3-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the atmega8515 as listed on page 74. reset reset input. a low level on this pin for longer than the minimu m pulse length will gener- ate a reset, even if the clock is not running. the minimum pulse length is given in table 18 on page 46. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. xtal2 output from the invert ing oscillator amplifier.
6 atmega8515(l) 2512js?avr?10/06 resources a comprehensive set of development tools, application notes and datasheets are avail- able for download on http://www.atmel.com/avr.
7 atmega8515(l) 2512js?avr?10/06 about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit defini- tions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documentation for more details.
8 atmega8515(l) 2512js?avr?10/06 register summary notes: 1. refer to the usart description for details on how to access ubrrh and ucsrc. 2. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f ($5f) sreg i t h s v n z c 10 $3e ($5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 12 $3d ($5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 12 $3c ($5c) reserved - $3b ($5b) gicr int1 int0 int2 - - - ivsel ivce 57, 78 $3a ($5a) gifr intf1 intf0 intf2 - - - - -79 $39 ($59) timsk toie1 ocie1a ocie1b - ticie1 - toie0 ocie0 93, 124 $38 ($58) tifr tov1 ocf1a ocf1b -icf1 - tov0 ocf0 93, 125 $37 ($57) spmcr spmie rwwsb - rwwsre blbset pgwrt pgers spmen 170 $36 ($56) emcucr sm0 srl2 srl1 srl0 srw01 srw00 srw11 isc2 29,42,78 $35 ($55) mcucr sre srw10 se sm1 isc11 isc10 isc01 isc00 29,41,77 $34 ($54) mcucsr - -sm2 - wdrf borf extrf porf 41,49 $33 ($53) tccr0 foc0 wgm00 com01 com00 wgm01 cs02 cs01 cs00 91 $32 ($52) tcnt0 timer/counter0 (8 bits) 93 $31 ($51) ocr0 timer/counter0 output compare register 93 $30 ($50) sfior - xmbk xmm2 xmm1 xmm0 pud - psr10 31,66,96 $2f ($4f) tccr1a com1a1 com1a0 com1b1 com1b0 foc1a foc1b wgm11 wgm10 119 $2e ($4e) tccr1b icnc1 ices1 - wgm13 wgm12 cs12 cs11 cs10 122 $2d ($4d) tcnt1h timer/counter1 - counter register high byte 123 $2c ($4c) tcnt1l timer/counter1 - counter register low byte 123 $2b ($4b) ocr1ah timer/counter1 - output compare register a high byte 123 $2a ($4a) ocr1al timer/counter1 - output compare register a low byte 123 $29 ($49) ocr1bh timer/counter1 - output compare register b high byte 123 $28 ($48) ocr1bl timer/counter1 - output compare register b low byte 123 $27 ($47) reserved - - $26 ($46) reserved - - $25 ($45) icr1h timer/counter1 - input capture register high byte 124 $24 ($44) icr1l timer/counter1 - input capture register low byte 124 $23 ($43) reserved - - $22 ($42) reserved - - $21 ($41) wdtcr - - - wdce wde wdp2 wdp1 wdp0 51 $20 (1) ($40) (1) ubrrh ursel - - - ubrr[11:8] 159 ucsrc ursel umsel upm1 up m0 usbs ucsz1 ucsz0 ucpol 157 $1f ($3f) eearh - - - - - - -eear8 19 $1e ($3e) eearl eeprom address register low byte 19 $1d ($3d) eedr eeprom data register 20 $1c ($3c) eecr - - - - eerie eemwe eewe eere 20 $1b ($3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 75 $1a ($3a) ddra dda7 dda6 dda 5 dda4 dda3 dda2 dda1 dda0 75 $19 ($39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 75 $18 ($38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 75 $17 ($37) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 75 $16 ($36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 75 $15 ($35) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 75 $14 ($34) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 75 $13 ($33) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 76 $12 ($32) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 76 $11 ($31) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 76 $10 ($30) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 76 $0f ($2f) spdr spi data register 133 $0e ($2e) spsr spif wcol - - - - - spi2x 133 $0d ($2d) spcr spie spe dord mstr cpol cpha spr1 spr0 131 $0c ($2c) udr usart i/o data register 155 $0b ($2b) ucsra rxc txc udre fe dor pe u2x mpcm 155 $0a ($2a) ucsrb rxcie txcie udri e rxen txen ucsz2 rxb8 txb8 156 $09 ($29) ubrrl usart baud rate register low byte 159 $08 ($28) acsr acd acbg aco aci acie acic acis1 acis0 164 $07 ($27) porte - - - - - porte2 porte1 porte0 76 $06 ($26) ddre - - - - - dde2 dde1 dde0 76 $05 ($25) pine - - - - - pine2 pine1 pine0 76 $04 ($24) osccal oscillator calibration register 39
9 atmega8515(l) 2512js?avr?10/06 3. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instruction s work with registers $00 to $1f only.
10 atmega8515(l) 2512js?avr?10/06 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd $ff ? rd z,c,n,v 1 neg rd two?s complement rd $00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? ($ff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2
11 atmega8515(l) 2512js?avr?10/06 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 mcu control instructions mnemonics operands description operation flags #clocks
12 atmega8515(l) 2512js?avr?10/06 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 mnemonics operands description operation flags #clocks
13 atmega8515(l) 2512js?avr?10/06 ordering information note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities.. 2. pb-free packaging alternative, complies to the european dire ctive for restriction of hazardous substances (rohs direc- tive).also halide free and fully green. speed (mhz) power supply ordering code package (1) operation range 8 2.7 - 5.5v atmega8515l-8ac atmega8515l-8pc atmega8515l-8jc atmega8515l-8mc (2) 44a 40p6 44j 44m1 commercial ( 0 c to 70 c) atmega8515l-8ai atmega8515l-8pi atmega8515l-8ji atmega8515l-8mi atmega8515l-8au (2) atmega8515l-8pu (2) ATMEGA8515L-8JU (2) atmega8515l-8mu (2) 44a 40p6 44j 44m1 44a 40p6 44j 44m1 industrial (-4 0 c to 85 c) 16 4.5 - 5.5v atmega8515-16ac atmega8515-16pc atmega8515-16jc atmega8515-16mc 44a 40p6 44j 44m1 commercial ( 0 c to 70 c) atmega8515-16ai atmega8515-16pi atmega8515-16ji atmega8515-16mi atmega8515-16au (2) atmega8515-16pu (2) atmega8515-16ju (2) atmega8515-16mu (2) 44a 40p6 44j 44m1 44a 40p6 44j 44mi industrial (-4 0 c to 85 c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 40p6 40-lead, 0.600? wide, plastic dual inline package (pdip) 44j 44-lead, plastic j-leaded chip carrier (plcc) 44m1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, quad flat no-lead/micro lead frame package (qfn/mlf)
14 atmega8515(l) 2512js?avr?10/06 packaging information 44a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
15 atmega8515(l) 2512js?avr?10/06 40p6 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 52.070 ? 52.578 note 2 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 2 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
16 atmega8515(l) 2512js?avr?10/06 44j notes: 1. this package conforms to jedec reference ms-018, variation ac. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.986 ? 16.002 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-lead, plastic j-leaded chip carrier (plcc) b 44j 10/04/01 2325 orchard parkway san jose, ca 95131 title drawing no. r rev.
17 atmega8515(l) 2512js?avr?10/06 44m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44m1 , 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, g 44m1 5/27/06 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 a3 0.25 ref b 0.18 0.23 0.30 d d2 5.00 5.20 5.40 6.90 7.00 7.10 6.90 7.00 7.10 e e2 5.00 5.20 5.40 e 0.50 bsc l 0.59 0.64 0.69 k 0.20 0.26 0.41 note: jedec standard mo-220, fig. 1 (saw singulation) vkkd-3. top view s ide view bottom view d e marked pin# 1 id e2 d2 b e pin #1 corner l a1 a3 a seating plane pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 1 2 3 5.20 mm exposed pad, micro lead frame package (mlf)
18 atmega8515(l) 2512js?avr?10/06 errata the revision letter in this section refers to the revision of the atmega8515 device. atmega8515(l) rev. c and d 1. first analog comparator conversion may be delayed if the device is powered by a slow rising vcc, the first analog comparator conver- sion will take longer than ex pected on some devices. problem fix/workaround when the device has been powered or reset, disable then enable the analog com- parator before the first conversion.
19 atmega8515(l) 2512js?avr?10/06 datasheet revision history please note that the referring page numbers in this section are referring to this docu- ment. the referring revision in this section are referring to the document revision. rev. 2512j-10/06 1. updated top/bottom description for all timer/counters fast pwm mode. 2. updated ?errata? on page 18. rev. 2512i-08/06 1. updated ?ordering information? on page 13. rev. 2512h-04/06 1. added ?resources? on page 6. 2. updated cross reference in ?phase correct pwm mode? on page 113. 3. updated ?timer/counter interrupt mask register ? timsk(1)? on page 124. 4. updated ?serial peripheral interface ? spi? on page 126. 5. removed obsolete section of ?calibration byte? on page 181. 6. updated table 10 on page 38, table 52 on page 120, table 94 on page 196 and table 96 on page 199. rev. 2512g-03/05 1. mlf-package alternative changed to ?quad flat no-lead/micro lead frame package qfn/mlf?. 2. updated ?electrical characteristics? on page 197 3. updated ?ordering information? on page 13. rev. 2512e-09/03 1. updated ?calibrated internal rc oscillator? on page 39. rev. 2512e-09/03 1. removed ?preliminary? from the datasheet. 2. updated table 18 on page 46 and ?absolute maximum ratings? and ?dc characteristics? in ?electrical characteristics? on page 197. 3. updated chapter ?atmega8515 typical characteristics? on page 207. rev. 2512d-02/03 1. added ?eeprom write during powe r-down sleep mode ? on page 23. 2. improved the description in ?phase correct pwm mode? on page 88. 3. corrected ocn waveforms in figure 53 on page 111. 4. added note under ?filling the temporar y buffer (page loading)? on page 173 about writing to the eeprom during an spm page load. 5. updated table 93 on page 195. 6. updated ?packaging information? on page 14.
20 atmega8515(l) 2512js?avr?10/06 rev. 2512c-10/02 1. added ?using all locations of external memory smaller than 64 kb? on page 31. 2. removed all tbd. 3. added description about calibration values for 2, 4, and 8 mhz. 4. added variation in frequency of ?external clock? on page 40. 5. added note about v bot , table 18 on page 46. 6. updated about ?unconnected pins? on page 64. 7. updated ?16-bit timer/counter1? on page 97, table 51 on page 119 and table 52 on page 120. 8. updated ?enter programming mode? on page 184, ?chip erase? on page 184, figure 77 on page 187, and figure 78 on page 188. 9. updated ?electrical characteristics? on page 197, ?external clock drive? on page 199, table 96 on page 199 and table 97 on page 200, ?spi timing char- acteristics? on page 200 and table 98 on page 202. 10. added ?errata? on page 18. rev. 2512b-09/02 1. changed the endurance on the flash to 10,000 write/erase cycles. rev. 2512a-04/02 1. initial.
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